1. Field of the Invention
This invention relates to a memory control device. More particularly, this invention relates to a control device used between two systems that each is based on different data format from the other's for converting a format of an input data into any adequate format to produce an output data having the converted format.
2. Description of the Invention
Conventionally, synchronous digital terminal equipment has been used as a hardware in a communication network. The term "synchronous digital terminal lequipment" used herein is a general term indicating a set of devices each of which is capable of receiving a digital signal supplied from a time division switch or other data signal lines and transmitting the received digital signal to a transmission path or vise versa. The synchronous digital terminal equipment comprises a time slot interchanger (TSI) unit performing a communication line establishing function. This TSI unit interchanges time slots on a digital multiple signal supplied from the communication path or a signal source without decomposing it physically into individual channels, whereby converting the data format of the input signal into that suitable for an output signal.
An example of this format conversion is described in conjunction with FIG. 9. In FIG. 9, an input data (DATA IN) is transmitted as a sequence of frames (fixed length data). Each frame is assumed to consist of sixteen channels (unit data) transmitted from two or more transmitting terminals. Each channel corresponds to one time slot. The channels transmitted from the identical transmitting terminal are identified by the same alphabet. In addition, the channels identified by the same alphabets are also identified by numerals with time. For example, "A1" indicates that the channel identified by it is the channel transmitted first from a transmitting terminal A. The frame of the input data (DATA IN) has a format consisting of the channels in which those identified by the same alphabet are collected together. More specifically, the channels identified by the same alphabet are sequenced in the numerical order. This sequence of channels is followed by another sequence of channels identified by the same alphabet. In this way, the sequence of channels follows in the alphabetical order. The TSI unit converts the format of the input data depending on a format suitable for the receiving system. More specifically, the TSI unit converts the format of the input data (DATA IN) into a format, as shown in an output data (DATA OUT) in this figure, where the channels bearing the same numeral are collected together and sequences of the channels bearing the same numeral are aligned in the alphabetical order. The above mentioned conversion is referred to as a format conversion or an interchange of channel orders. In FIG. 9, FP represents synchronous pulses indicating the start of each frame of the input data (DATA IN).
A conventional memory control device applicable to the above mentioned format conversion is described in conjunction with a block diagram shown in FIG. 10. First, connection of the individual blocks in FIG. 10 is described. An input data (DATA1IN) is supplied to this memory control device through an input line .phi.1 and is supplied in turn to a data input and output terminal of a random access memory (RAM) 501 through a high-impedance control unit 504. A synchronous pulse (FP1) corresponding to this input data (DATA1IN) is supplied to this memory control device through a signal line .phi.2 and is supplied in turn to an address generating unit 502 as well as a RAM control pulse generating unit 503. The address generating device 502 is connected to an address input terminal of the RAM 501. The RAM control pulse generating unit 503 is connected to each of control pulse input terminals of the RAM 501, a control terminal of the high-impedance control 504 and a clock pulse (CK) input terminal of a flip-flop 505. D input terminal of the flip-flop 505 is connected to an input and output terminal of the RAM 504.
Next, function of each block in FIG. 10 is described.
The high-impedance control unit 504 varies impedance conditions on the input data (DATA1IN) in response to control pulses supplied from the RAM control pulse generating unit 503. The high-impedance control unit 504 whereby controls supply of the input data (DATA1IN) to the RAM 501. More specifically, the impedance is decreased to allow passage of the input data (DATA1IN) during writing of the input data (DATA1IN) into the RAM 501. On the other hand, the impedance is increased to impede pass of the input data (DATA1IN) during reading the data stored in the RAM 501.
The RAM 501 stores the input data (DATA1IN) received through the input and output terminal according to a writing address. The writing address is an address designated by the address generating unit 502, indicating where the data should be written in the RAM. In addition, the RAM 501 supplies the stored data to the input and output terminal according to a reading address. The reading address is an address designated by the address generating unit 502, indicating a read position in the RAM. The RAM 501 performs writing operation in synchronism the control pulses supplied from the RAM control pulse generating unit 503. The address generating unit 502 designates addresses. The address generating unit 502 changes a value of the address to be designated according to a given order at every time when it receives the synchronous pulse (FP1).
The flip-flop 505 receives the read data from the RAM 501 through its D input terminal. The flip-flop 505 receives the control signal supplied from the RAM control pulse generating unit 503 through the CP input terminal. An output data (DATA1OUT) is supplied from the output terminal of the flip-flop 505. The flip-flop 505 thus serves as a D flip-flop.
The RAM control pulse generating unit 503 generates control pulses for the RAM 501, the high-impedance control unit 504 and the flip-flop 505 at a predetermined timing at every time in response to the synchronous pulse (FP1).
Next, operation of the conventional memory control device so constructed is described.
First, in writing the input data (DATA1IN) into the RAM 501, the RAM control pulse generating unit 503 supplies, in response to the synchronous pulse (FP1), the writing pulse to the RAM 501 and renders the high-impedance control unit 504 low in impedance. This allows writing of the input data (DATA1IN) into the RAM 501. In addition, the RAM control pulse generating unit 503 stops clock pulse input to the flip-flop 505. This prevents the input data (DATA1IN) from being produced outside the device as it is. At the same time, the address generating unit 502 designates the writing address while varing the value of the address according to a predetermined order in response to input of the synchronous pulses (FP1). As a result, the input data (DATA1IN) is written into the RAM 501 in the order as shown in, for example, DATA IN in FIG. 10.
Next, in reading the data stored in the RAM 501, the RAM control pulse generating unit 503 stops the writing pulses to the RAM 501 and renders the high-impedance control unit 504 high in impedance. This hinders passage of the input data (DATA1IN) in the high-impedance control unit 504. In addition, the RAM control pulse generating unit 503 supplies clock pulses to the flip-flop at a predetermined fixed cycle. This allows output of the read data. At the same time, the address generating unit 502 designates the reading address while varing the value of the address according to the order different from the order of writing. As a result, the data written in the RAM is supplied as the output data (DATA1OUT) to the outside the device through the flip-flop 505 in the order shown in, for example, DATA OUT in FIG. 9. Switching of writing and reading may be made in various ways, of which description is omitted herein.
Typically, two or more sequences of data should be processed simultaneously in the TSI unit. The term "two or more sequences of data" used herein means a plurality of data supplied separately from the parallel input lines .phi.1. However, in the above mentioned conventional memory control device, only one sequence of data is allowed to be supplied and processed for a single device. Accordingly, a plurality of data control devices having the identical structure should be provided as shown in FIG. 10 for processing a plural sequences of data. In such a case, plurality of circuits such as the RAMs and RAM control pulse generating units should be provided, which enlarges the dimension and scale of the hardware that can only be achieved at an extremely high cost.